1. Field of the Invention
The present invention relates to parallel processing systems, and in particular to a method and system for configuring a massively parallel processing system.
2. Description of the Related Art
Parallel processing is considered an advantageous approach for increasing processing speeds in computer systems. Parallel processing can provide powerful communications and computer systems which can handle complex problems and manipulate large databases quickly and reliably.
One example of parallel processing can be found in U.S. Pat. No. 4,412,285, issued Oct. 25, 1983, to Neches et al., incorporated by reference herein. This patent describes a system using a sorting network to intercouple multiple processors so as to distribute priority messages to all processors. Another example of parallel processing can be found in U.S. Pat. No. 5,321,813 issued Jun. 14, 1994 to McMillen et al., which reference is also hereby incorporated by reference herein.
One of the difficulties associated with parallel processing systems involves the logical configuration of such systems. Prior art parallel processing systems are typically configured with the use of five inter-dependent services for: (1) registering nodes, (2) examining local and global net states, (3) merging global parallel processing info with local info, (4) freezing the selected parallel processing configuration, and (5) selecting or dropping parallel processing nodes. On very large systems, these methods can be unreliable. Further, in some cases, use of these methods can render some of the drivers and interfaces of the massively parallel processing system unusable.
From the foregoing, it can be seen that there is a need for a simplified method for logically configuring parallel processing systems. The present invention satisfies this need.
To address the requirements described above, the present invention discloses a simplified method, apparatus, and article of manufacture for configuring a parallel processing system.
The present invention uses a voting process to logically configure the parallel processing system. Each node in the system votes for a node that it believes is the best candidate to control the configuration process. The controlling node, also called a coordinator, selects the configuration and distributes the information to all other nodes in the system. Prior art methods of configuring the parallel processing system were less reliable when applied to very large systems and did not support BLLI Bynet drivers and Bynet QBIC interfaces. This invention provides a well-structured and dependable process for configuring massively parallel processors. This invention is particularly useful in the logical configuration a parallel processing system to run the parallel database extensions of the TERADATA database.
More specifically, the method comprises the steps of selecting one of the interconnected nodes as a coordinator node, and the remaining nodes as non-coordinator nodes, the coordinator node for controlling the configuration of the parallel processing system; defining, in the coordinator node, a parallel processing system configuration having member nodes; and multicasting the parallel processing system configuration to the nodes.
The apparatus comprises a means for performing the steps described above, and the article of manufacture comprises a program storage device tangibly embodying computer instructions for performing the above method steps.
Using the steps outlined above, the foregoing invention allows a parallel processing system to be configured with fewer operations and fewer configuration services than possible in the prior art. Specifically, the number of configuration services to be reduced from five to two (one for selecting the coordinator, and the second for configuring the parallel processing system), simplifying software and hardware design, and improving maintainability and reliability as well.